In a Flash memory chip, the user sends commands to the Flash to operate the memory using the data lines DQs. The commands are interpreted and routed for execution to the remaining chip by a block of logic called a command user interface (CUI). The CUI is a commands interpreter that accepts commands from the user. Such commands may include by way of example only and not by way of limitation “read array,” “read configuration register,” “program,” “erase,” “suspend,” and the like. The CUI also controls the execution of the received commands. The commands are entered using multiple cycle clock operation.
In Flash memory chips in which the memory cells are organized into a single array, the CUI controls all of the operations that can be executed on the single memory partition. Recently, later generation Flash memories include cell arrays organized into two partitions, on which concurrent operations can be executed. In these memories, one operation may be in execution in one partition, while the other partition executes a different operation. Due to the two partition architecture, time consuming operations, such as erase, are capable of execution in one partition while at the same time, data can be retrieved from the other partition not involved in the erase operation.
CUIs are typically implemented using synthesized logic. When a Flash architecture with two partitions requires concurrent operations, the CUI increases dramatically in size to accommodate the increased number of commands needed to operate both partitions. A typical CUI for a two partition array includes a word line decoder, a read only memory (ROM), and latches. Because the two partitions must be managed independently for concurrent operations, the number of inputs and outputs of the CUI, and hence the size of the ROM and the associated ROM circuitry, increases accordingly. The silicon area occupied by the CUI becomes too large, an in turn increases the overall cost of the chip. The size increase is further emphasized for chips using more than two partitions, in which the number of inputs, outputs, and the complexity of associated circuitry, all continue to increase.
It would be desirable to provide a smaller CUI architecture to manage concurrent operations in a memory having two or more partitions.